Characterization of the devices in the latest FinFET technology nodes accounting for the surrounding layout

The goal of the research is modeling the effect that the cuts on the Polysilicon on the neighborhood gates have on the performance of the devices, identifying the type of stress caused by specific layout patterns


  • Primary: Luigi Colalongo
  • Other advisors: Sharad Saxena


Short Bio

My name is Angelo Rossoni and I am a tech-savvy Micro Electronics Engineer with a 23-year track record designing, testing and developing testing structures for VLSI process, systems and devices. Collaborative team leader recognized for displaying perseverance while working through complex problems to satisfactory resolution. I graduated from the Universita’ degli Studi di Brescia in 2000 with a master’s degree in Electronic Engineer.